Hardware Analysis Community Forums http://www.hardwareanalysis.com/content/topic/727/ 2009-01-08T19:51:26-05:00 http://www.hardwareanalysis.com/content/topic/727/ http://media.hardwareanalysis.com/halogo.gif text/html 2002-02-05T17:29:51-05:00 Dan Mepham http://www.hardwareanalysis.com/content/topic/727/#6085 Good point. Observed latency is likely to decrease when using a synchronous setting, definitely.<br /> text/html 2002-02-05T17:18:08-05:00 Robert Kropiewnicki http://www.hardwareanalysis.com/content/topic/727/#0 Dan,<br /> <br /> I think your conclusions on the Cachemem results may be off target a touch.<br /> <br /> Here's the quote in question:<br /> <br /> &quot;One interesting item to note here is that the performance of the 500FSB/266MEM platform is closer to that of the 500/333 than the 500/266. This indicates that the latency seen by Cachemem is more affected by Front Side Bus bandwidth than by memory bandwidth.&quot;<br /> <br /> Going back to your mentioning that the 500FSB/266MEM platform is actually running at 500FSB/250MEM, I would submit that the added FSB bandwidth is not the only factor and may not even be the main factor in the difference. The 500FSB/250MEM is actually running in sync where if it was actually running at 500FB/266MEM, it would be running asynch. As we've seen with many other platforms, the memory bus running asynch to the FSB can incur significant penalties.